PLUS
ProASIC
Flash Family FPGAs
Asynchronous FIFO Read
t
RPRDA
t
t
RDH
RDL
Cycle Start
RB = (RDB+RBLKB)
(Empty inhibits read)
RDATA
RPE
WB
EMPTY
FULL
EQTH, GETH
t
t
t
, t
RDWRS
ERDH FRDH
t
, t
ORDH
ERDA FRDA
t
t
RPRDH
THRDH
t
t
ORDA
THRDA
t
RPRDA
t
t
RDL
RDH
t
RDCYC
Note: The plot shows the normal operation status.
Figure 1-43 • Asynchronous FIFO Read
Table 1-61 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max. Units
Notes
ERDH, FRDH, Old EMPTY, FULL, EQTH, & GETH valid hold
0.5
ns
Empty/full/thresh are invalid from the end of
hold until the new access is complete
THRDH
time from RB ↑
ERDA
New EMPTY access from RB ↑
FULL↓ access from RB ↑
New DO access from RB ↓
Old DO valid from RB ↓
Read cycle time
3.01
3.01
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FRDA
ORDA
ORDH
RDCYC
RDWRS
3.0
1.0
7.5
3.02
WB ↑, clearing EMPTY, setup to
RB ↓
Enabling the read operation
Inhibiting the read operation
Inactive
RDH
RB high phase
3.0
3.0
9.5
RDL
RB low phase
Active
RPRDA
RPRDH
THRDA
Notes:
New RPE access from RB ↓
Old RPE valid from RB ↓
EQTH or GETH access from RB↑
4.0
4.5
1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.
2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns.
3. All –F speed grade devices are 20% slower than the standard numbers.
v5.2
1-67
ACTEL [ Actel Corporation ]
