PLUS
ProASIC
Flash Family FPGAs
Asynchronous FIFO Write
Cycle Start
WB = (WRB+WBLKB)
WDATA
WPE
(Full inhibits write)
RB
FULL
EMPTY
EQTH, GETH
t
t
WRRDS
DWRH
t
t
WPDH
WPDA
t
DWRS
t
t
, t
EWRH FWRH
, t
EWRA FWRA
t
t
THWRH
THWRA
t
t
WRL
WRH
t
WRCYC
Note: The plot shows the normal operation status.
Figure 1-44 • Asynchronous FIFO Write
Table 1-62 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
DWRH
Description
DI hold from WB ↑
Min.
1.5
Max.
Units
ns
Notes
DWRS
DI setup to WB ↑
DI setup to WB ↑
0.5
ns
PARGEN is inactive
PARGEN is active
DWRS
2.5
ns
EWRH, FWRH, Old EMPTY, FULL, EQTH, & GETH valid hold
0.5
ns
Empty/full/thresh are invalid from the end
of hold until the new access is complete
THWRH
time after WB ↑
EWRA
EMPTY ↓ access from WB ↑
New FULL access from WB ↑
EQTH or GETH access from WB ↑
WPE access from DI
3.01
3.01
4.5
ns
ns
ns
ns
ns
ns
ns
FWRA
THWRA
WPDA
WPDH
WRCYC
WRRDS
3.0
WPE is invalid while PARGEN is active
WPE hold from DI
1.0
1.0
Cycle time
7.5
3.02
RB ↑, clearing FULL, setup to
WB ↓
Enabling the write operation
Inhibiting the write operation
Inactive
WRH
WRL
WB high phase
WB low phase
3.0
3.0
ns
ns
Active
Notes:
1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns.
2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns.
3. All –F speed grade devices are 20% slower than the standard numbers.
4. After FIFO reset, WRB needs an initial falling edge prior to any write actions.
1-68
v5.2
ACTEL [ Actel Corporation ]
