PLUS
ProASIC
Flash Family FPGAs
TMS
Test Mode Select
Pin Description
The TMS pin controls the use of boundary-scan circuitry.
This pin has an internal pull-up resistor.
User Pins
TCK
Test Clock
I/O
User Input/Output
Clock input pin for boundary scan (maximum 10 MHz). Actel
recommends adding a nominal 20 kΩ pull-up resistor to this
pin.
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with standard LVTTL and LVCMOS
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
TDI
Test Data In
Serial input for boundary scan. A dedicated pull-up
resistor is included to pull this pin high when not being
driven.
NC
No Connect
To maintain compatibility with other Actel ProASICPLUS
products, it is recommended that this pin not be
connected to the circuitry on the board.
TDO
Test Data Out
Serial output for boundary scan. Actel recommends
adding a nominal 20kΩ pull-up resistor to this pin.
GL
Global Pin
TRST
Test Reset Input
Low skew input pin for clock or other global signals. This
pin can be configured with an internal pull-up resistor.
When it is not connected to the global network or the
clock conditioning circuit, it can be configured and used
as a normal I/O.
Asynchronous, active-low input pin for resetting
boundary-scan circuitry. This pin has an internal pull-up
resistor. For more information, please refer to Power-up
Behavior of ProASICPLUS Devices application note.
GLMX
Global Multiplexing Pin
Special Function Pins
Low skew input pin for clock or other global signals. This
pin can be used in one of two special ways (refer to
Actel’s Using ProASICPLUS Clock Conditioning Circuits).
RCK
Running Clock
A free running clock is needed during programming if
the programmer cannot guarantee that TCK will be
uninterrupted. If not used, this pin has an internal pull-
up and can be left floating.
When the external feedback option is selected for the
PLL block, this pin is routed as the external feedback
source to the clock conditioning circuit.
In applications where two different signals access the
same global net at different times through the use of
GLMXx and GLMXLx macros, this pin will be fixed as one
of the source pins.
NPECL
User Negative Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
This pin can be configured with an internal pull-up
resistor. When it is not connected to the global network
or the clock conditioning circuit, it can be configured and
used as any normal I/O. If not used, the GLMXx pin will
be configured as an input with pull-up.
PPECL
User Positive Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
AVDD
PLL Power Supply
Analog VDD should be VDD (core voltage) 2.5 V (nominal)
and be decoupled from GND with suitable decoupling
capacitors to reduce noise. For more information, refer
to Actel’s Using ProASICPLUS Clock Conditioning Circuits
application note. If the clock conditioning circuitry is not
used in a design, AVDD can either be left floating or tied
to 2.5 V.
Dedicated Pins
GND
Ground
Common ground supply voltage.
V
Logic Array Power Supply Pin
DD
2.5 V supply voltage.
AGND
PLL Power Ground
V
I/O Pad Power Supply Pin
DDP
The analog ground can be connected to the system
ground. For more information, refer to Actel’s Using
ProASICPLUS Clock Conditioning Circuits application note.
If the PLLs or clock conditioning circuitry are not used in
a design, AGND should be tied to GND.
2.5 V or 3.3 V supply voltage.
v5.2
1-73
ACTEL [ Actel Corporation ]
