PLUS
ProASIC
Flash Family FPGAs
Asynchronous FIFO Full and Empty Transitions
The asynchronous FIFO accepts writes and reads while
not full or not empty. When the FIFO is full, all writes are
inhibited. Conversely, when the FIFO is empty, all reads
are inhibited. A problem is created if the FIFO is written
to during the transition from full to not full, or read
during the transition from empty to not empty. The
exact time at which the write or read operation changes
from inhibited to accepted after the read (write) signal
which causes the transition from full or empty to not full
or not empty is indeterminate. For slow cycles, this
indeterminate period starts 1 ns after the RB (WB)
transition, which deactivates full or not empty and ends
3 ns after the RB (WB) transition. For fast cycles, the
indeterminate period ends 3 ns (7.5 ns – RDL (WRL)) after
the RB (WB) transition, whichever is later (Table 1-1 on
page 1-7).
The timing diagram for write is shown in Figure 1-38 on
page 1-62. The timing diagram for read is shown in
Figure 1-39 on page 1-63. For basic SRAM configurations,
see Table 1-13 on page 1-24. When reset is asserted, the
empty flag will be asserted, the counters will reset, the
outputs go to zero, but the internal RAM is not erased.
Enclosed Timing Diagrams – FIFO Mode:
•
•
•
"Asynchronous FIFO Read" section on page 1-67
"Asynchronous FIFO Write" section on page 1-68
"Synchronous FIFO Read, Access Timed Output
Strobe (Synchronous Transparent)" section on
page 1-69
•
"Synchronous FIFO Read, Pipeline Mode Outputs
(Synchronous Pipelined)" section on page 1-70
•
•
"Synchronous FIFO Write" section on page 1-71
"FIFO Reset" section on page 1-72
Table 1-60 • Memory Block FIFO Interface Signals
FIFO Signal
WCLKS
Bits
In/Out
In
Description
1
Write clock used for synchronization on write side
Read clock used for synchronization on read side
Direct configuration implements static flag logic
Read block select (active Low)
RCLKS
1
8
1
1
1
1
9
1
2
2
In
LEVEL <0:7>*
RBLKB
In
In
RDB
In
Read pulse (active Low)
RESET
In
Reset for FIFO pointers (active Low)
WBLKB
In
Write block select (active Low)
DI<0:8>
WRB
In
Input data bits <0:8>, <8> will be generated if PARGEN is true
Write pulse (active Low)
In
FULL, EMPTY
EQTH, GEQTH*
Out
Out
FIFO flags. FULL prevents write and EMPTY prevents read
EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.
GEQTH is true when the FIFO holds (LEVEL) words or more
DO<0:8>
RPE
9
1
1
3
1
Out
Out
Out
In
Output data bits <0:8>
Read parity error (active High)
WPE
Write parity error (active High)
LGDEP <0:2>
PARODD
Configures DEPTH of the FIFO to 2 (LGDEP+1)
In
Selects Odd parity generation/detect when high, Even when low
Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be
possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that
indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL.
Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs.
v5.2
1-65
ACTEL [ Actel Corporation ]
