PLUS
ProASIC
Flash Family FPGAs
Synchronous Write and Asynchronous Read to the Same Location
RB, RADDR
NEW
NEWER
DO
OLD
WCLKS
t
t
ORDA
RAWCLKH
t
ORDH
t
OWRA
t
OWRH
t
RAWCLKS
Note: The plot shows the normal operation status.
Figure 1-40 • Synchronous Write and Asynchronous Read to the Same Location
Table 1-59 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
ORDA
Description
New DO access from RB ↓
Old DO valid from RB ↓
Min.
Max.
Units
ns
Notes
7.5
ORDH
3.0
ns
OWRA
New DO access from WCLKS ↓
Old DO valid from WCLKS ↓
RB ↓ or RADDR from WCLKS ↑
RB ↑ or RADDR from WCLKS ↓
3.0
ns
OWRH
0.5
ns
RAWCLKS
RAWCLKH
Notes:
5.0
5.0
ns
ns
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically
trigger a read operation which updates the read data.
2. Violation of RAWCLKS will disturb access to OLD data.
3. Violation of RAWCLKH will disturb access to NEWER data.
4. All –F speed grade devices are 20% slower than the standard numbers.
1-64
v5.2
ACTEL [ Actel Corporation ]
