PLUS
ProASIC
Flash Family FPGAs
Asynchronous Write and Read to the Same Location
RB, RADDR
NEW
NEWER
DO
OLD
WB = {WRB+WBLKB}
t
t
ORDA
RAWRH
t
ORDH
t
t
RAWRS
OWRA
t
OWRH
Note: The plot shows the normal operation status.
Figure 1-39 • Asynchronous Write and Read to the Same Location
Table 1-58 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
ORDA
Description
New DO access from RB ↓
Old DO valid from RB ↓
Min.
Max.
Units
Notes
7.5
ns
ns
ns
ns
ns
ns
ORDH
3.0
OWRA
New DO access from WB ↑
Old DO valid from WB ↑
RB ↓ or RADDR from WB ↓
RB ↑ or RADDR from WB ↑
3.0
OWRH
0.5
RAWRS
RAWRH
Notes:
5.0
5.0
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically
trigger a read operation which updates the read data. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more
information.
2. Violation or RAWRS will disturb access to the OLD data.
3. Violation of RAWRH will disturb access to the NEWER data.
4. All –F speed grade devices are 20% slower than the standard numbers.
v5.2
1-63
ACTEL [ Actel Corporation ]
