PLUS
ProASIC
Flash Family FPGAs
Asynchronous Write and Synchronous Read to the Same Location
t
t
CMH
CML
RCLKS
DO
New Data*
Last Cycle Data
WB = {WRB + WBLKB}
DI
t
WRCKS
t
BRCLKH
t
OCH
OCA
t
t
t
DWRRCLKS
DWRH
t
CCYC
* New data is read if WB ↓ occurs before setup time.
The stored data is read if WB ↓ occurs after hold time.
Note: The plot shows the normal operation status.
Figure 1-38 • Asynchronous Write and Synchronous Read to the Same Location
Table 1-57 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
CCYC
Description
Min.
7.5
Max.
Units
ns
Notes
Cycle time
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
WBRCLKS
WBRCLKH
OCH
WB ↓ to RCLKS ↑ setup time
WB ↓ to RCLKS ↑ hold time
Old DO valid from RCLKS ↑
New DO valid from RCLKS ↑
DI to RCLKS ↑ setup time
DI to WB ↑ hold time
–0.1
ns
7.0
3.0
ns
ns
OCA/OCH
Access Timed Output
displayed
for
OCA
7.5
0
ns
DWRRCLKS
DWRH
ns
1.5
ns
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write
signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be
read.
3. A setup or hold time violation will result in unknown output data.
4. All –F speed grade devices are 20% slower than the standard numbers.
1-62
v5.2
ACTEL [ Actel Corporation ]
