PLUS
ProASIC
Flash Family FPGAs
Synchronous SRAM Write
WCLKS
WRB, WBLKB
WADDR, DI
WPE
Cycle Start
t
, t
WRCH WBCH
t
, t
WRCS WBCS
t
, t
DCS WDCS
t
WPCH
t
, t
DCH WACH
t
WPCA
t
t
CML
CMH
t
CCYC
Note: The plot shows the normal operation status.
Figure 1-36 • Synchronous SRAM Write
Table 1-55 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
CCYC
CMH
Description
Min.
7.5
3.0
3.0
0.5
1.0
0.5
1.0
3.0
Max.
Units
ns
Notes
Cycle time
Clock high phase
ns
CML
Clock low phase
ns
DCH
DI hold from WCLKS ↑
DI setup to WCLKS ↑
ns
DCS
ns
WACH
WDCS
WPCA
WPCH
WADDR hold from WCLKS ↑
WADDR setup to WCLKS ↑
New WPE access from WCLKS ↑
Old WPE valid from WCLKS ↑
ns
ns
ns
WPE is invalid while
PARGEN is active
0.5
ns
WRCH, WBCH WRB & WBLKB hold from WCLKS ↑
WRCS, WBCS WRB & WBLKB setup to WCLKS ↑
Notes:
0.5
1.0
ns
ns
1. On simultaneous read and write accesses to the same location, DI is output to DO.
2. All –F speed grade devices are 20% slower than the standard numbers.
1-60
v5.2
ACTEL [ Actel Corporation ]
