PLUS
ProASIC
Flash Family FPGAs
Asynchronous SRAM Read, RDB Controlled
RB=(RDB+RBLKB)
DO
RPE
t
ORDH
t
RPRDH
t
ORDA
t
RPRDA
t
t
RDML
RDMH
t
RDCYC
Note: The plot shows the normal operation status.
Figure 1-35 • Asynchronous SRAM Read, RDB Controlled
Table 1-54 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
ORDA
Description
New DO access from RB ↓
Old DO valid from RB ↓
Read cycle time
Min.
Max.
Units
ns
Notes
7.5
ORDH
3.0
ns
RDCYC
RDMH
7.5
3.0
3.0
9.5
ns
RB high phase
ns
Inactive setup to new cycle
Active
RDML
RB low phase
ns
RPRDA
RPRDH
New RPE access from RB ↓
Old RPE valid from RB ↓
ns
3.0
ns
Note: All –F speed grade devices are 20% slower than the standard numbers.
v5.2
1-59
ACTEL [ Actel Corporation ]
