PLUS
ProASIC
Flash Family FPGAs
Asynchronous SRAM Read, Address Controlled, RDB=0
RADDR
DO
RPE
t
OAH
t
RPAH
t
OAA
t
RPAA
t
ACYC
Note: The plot shows the normal operation status.
Figure 1-34 • Asynchronous SRAM Read, Address Controlled, RDB=0
Table 1-53 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B
Symbol txxx
ACYC
Description
Read cycle time
Min.
7.5
Max.
Units
ns
Notes
OAA
New DO access from RADDR stable
Old DO hold from RADDR stable
New RPE access from RADDR stable
Old RPE hold from RADDR stable
7.5
ns
OAH
3.0
3.0
ns
RPAA
10.0
ns
RPAH
ns
Note: All –F speed grade devices are 20% slower than the standard numbers.
1-58
v5.2
ACTEL [ Actel Corporation ]
