PLUS
ProASIC
Flash Family FPGAs
Asynchronous SRAM Write
WADDR
WRB, WBLKB
DI
WPE
t
t
AWRS
AWRH
t
t
DWRH
WPDH
t
WPDA
t
DWRS
t
t
WRMH
WRML
t
WRCYC
Note: The plot shows the normal operation status.
Figure 1-33 • Asynchronous SRAM Write
Table 1-52 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B
Symbol txxx
AWRH
Description
WADDR hold from WB ↑
Min.
1.0
0.5
1.5
0.5
2.5
3.0
Max.
Units
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AWRS
WADDR setup to WB ↓
DI hold from WB ↑
DI setup to WB ↑
DI setup to WB ↑
WPE access from DI
WPE hold from DI
Cycle time
DWRH
DWRS
PARGEN is inactive.
PARGEN is active.
DWRS
WPDA
WPE is invalid, while PARGEN is
active.
WPDH
1.0
WRCYC
WRMH
WRML
7.5
3.0
3.0
WB high phase
Inactive
Active
WB low phase
Note: All –F speed grade devices are 20% slower than the standard numbers.
v5.2
1-57
ACTEL [ Actel Corporation ]
