PLUS
ProASIC
Flash Family FPGAs
Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
RCLKS
Cycle Start
RBD, RBLKB
New Valid
RADDR
Address
Old Data Out
New Valid Data Out
DO
RPE
t
RACS
t
RDCS
t
RDCH
t
RACH
t
OCH
t
RPCH
t
t
CMH
CML
t
OCA
t
RPCA
t
CCYC
Note: The plot shows the normal operation status.
Figure 1-31 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Table 1-50 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
CCYC
CMH
Description
Min.
7.5
Max.
Units
ns
Notes
Cycle time
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RADDR hold from RCLKS ↑
RADDR setup to RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
7.5
ns
OCH
3.0
ns
RACH
RACS
0.5
1.0
0.5
1.0
9.5
ns
ns
RDCH
RDCS
ns
ns
RPCA
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
ns
RPCH
3.0
ns
Note: All –F speed grade devices are 20% slower than the standard numbers.
v5.2
1-55
ACTEL [ Actel Corporation ]
