PLUS
ProASIC
Flash Family FPGAs
Embedded Memory Specifications
This section discusses ProASICPLUS SRAM/FIFO embedded
memory and its interface signals, including timing
diagrams that show the relationships of signals as they
pertain to single embedded memory blocks (Table 1-49).
Table 1-12 on page 1-23 shows basic SRAM and FIFO
configurations. Simultaneous read and write to the same
location must be done with care. On such accesses the DI
bus is output to the DO bus. Refer to the ProASICPLUS
RAM and FIFO Blocks application note for more
information.
•
"Asynchronous SRAM Read, RDB Controlled"
section on page 1-59
•
•
"Synchronous SRAM Write"
Embedded Memory Specifications
The difference between synchronous transparent and
pipeline modes is the timing of all the output signals
from the memory. In transparent mode, the outputs will
change within the same clock cycle to reflect the data
requested by the currently valid access to the memory. If
clock cycles are short (high clock speed), the data
requires most of the clock cycle to change to valid values
(stable signals). Processing of this data in the same clock
cycle is nearly impossible. Most designers add registers at
all outputs of the memory to push the data processing
into the next clock cycle. An entire clock cycle can then
be used to process the data. To simplify use of this
Enclosed Timing Diagrams—SRAM Mode:
•
"Synchronous SRAM Read, Access Timed Output
Strobe (Synchronous Transparent)" section on
page 1-55
•
"Synchronous SRAM Read, Pipeline Mode Outputs
(Synchronous Pipelined)" section on page 1-56
memory
setup,
suitable
registers
have
been
•
•
"Asynchronous SRAM Write" section on page 1-57
implemented as part of the memory primitive and are
available to the user in the synchronous pipeline mode.
In this mode, the output signals will change shortly after
the second rising edge, following the initiation of the
read access.
"Asynchronous SRAM Read, Address Controlled,
RDB=0" section on page 1-58
Table 1-49 • Memory Block SRAM Interface Signals
SRAM Signal
WCLKS
RCLKS
Bits
1
In/Out
In
Description
Write clock used on synchronization on write side
1
In
Read clock used on synchronization on read side
Read address
RADDR<0:7>
RBLKB
8
In
1
In
True read block select (active Low)
True read pulse (active Low)
RDB
1
In
WADDR<0:7>
WBLKB
8
In
Write address
1
In
Write block select (active Low)
DI<0:8>
WRB
9
In
Input data bits <0:8>, <8> can be used for parity In
Negative true write pulse
1
In
DO<0:8>
RPE
9
Out
Out
Out
In
Output data bits <0:8>, <8> can be used for parity Out
Read parity error (active High)
1
WPE
1
Write parity error (active High)
PARODD
1
Selects Odd parity generation/detect when high, Even when low
Note: Not all signals shown are used in all modes.
1-54
v5.2
ACTEL [ Actel Corporation ]
