PLUS
ProASIC
Flash Family FPGAs
Global Input Buffer Delays
Table 1-37 • Worst-Case Commercial Conditions
VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C
1
2
Max. tINYH
Max. tINYL
Units
Macro Type
GL33
Description
Std.3
–F
Std.3
–F
3.3 V, CMOS Input Levels4, No Pull-up Resistor
3.3 V, CMOS Input Levels4, No Pull-up Resistor, Schmitt Trigger
PPECL Input Levels
1.0
1.2
1.2
1.2
1.1
1.3
1.3
1.3
ns
ns
ns
GL33S
1.0
1.1
PECL
1.0
1.1
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. Applies to Military ProASICPLUS devices.
4. LVTTL delays are the same as CMOS delays.
5. For LP Macros, VDDP=2.3 V for delays.
6. All –F parts are only available as commercial.
Table 1-38 • Worst-Case Commercial Conditions
VDDP = 2.3 V, VDD = 2.3 V, TJ = 70°C
1
2
Max. tINYH
Max. tINYL
Units
Macro Type
GL25LP
Description
2.5 V, CMOS Input Levels4, Low Power
2.5 V, CMOS Input Levels4, Low Power, Schmitt Trigger
Std.3
–F
Std.3
–F
1.1
1.2
1.6
1.0
1.3
1.1
ns
ns
GL25LPS
Notes:
1.3
1.0
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. Applies to Military ProASICPLUS devices.
4. LVTTL delays are the same as CMOS delays.
5. For LP Macros, VDDP=2.3 V for delays.
6. All –F parts are only available as commercial.
1-48
v5.2
ACTEL [ Actel Corporation ]
