PLUS
ProASIC
Max.
Flash Family FPGAs
Table 1-31 • Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 125°C for Military/MIL-STD-883
Max.
1
2
tDLH
tDHL
Macro Type
OB33PH
OB33PN
OB33PL
Description
Std.
2.1
2.5
2.7
2.7
3.3
3.3
Std.
2.3
3.2
3.5
4.3
4.7
6.1
Units
ns
3.3V, PCI Output Current, High Slew Rate
3.3V, High Output Current, Nominal Slew Rate
3.3V, High Output Current, Low Slew Rate
3.3V, Low Output Current, High Slew Rate
3.3V, Low Output Current, Nominal Slew Rate
3.3V, Low Output Current, Low Slew Rate
ns
ns
OB33LH
OB33LN
OB33LL
ns
ns
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
Table 1-32 • Worst-Case Military Conditions
VDDP = 2.3 V, VDD = 2.3V, 35 pF load, TJ = 125°C for Military/MIL-STD-883
Max.
tDLH
Max.
tDHL
1
2
Macro Type
Description
Std.
2.3
2.7
3.2
3.0
3.9
4.3
Std.
2.4
3.3
3.5
5.0
4.6
5.7
Units
ns
OB25LPHH
OB25LPHN
OB25LPHL
OB25LPLH
OB25LPLN
OB25LPLL
Notes:
2.5V, Low Power, High Output Current, High Slew Rate3
2.5V, Low Power, High Output Current, Nominal Slew Rate3
2.5V, Low Power, High Output Current, Low Slew Rate3
2.5V, Low Power, Low Output Current, High Slew Rate3
2.5V, Low Power, Low Output Current, Nominal Slew Rate3
2.5V, Low Power, Low Output Current, Low Slew Rate3
ns
ns
ns
ns
ns
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays.
v5.2
1-45