PLUS
ProASIC
Flash Family FPGAs
Input Buffer Delays
V
DDP
PAD
0 V
50%
50% 50%
VDD
Y
PAD
Y
GND
50%
IBx
t
t
INYH
INYL
Figure 1-28 • Input Buffer Delays
Table 1-33 • Worst-Case Commercial Conditions
VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C
1
2
Max. tINYH
Max. tINYL
Macro Type
IB33
Description
Std.
0.4
–F
Std.
0.6
–F
Units
ns
3.3 V, CMOS Input Levels3, No Pull-up Resistor
0.5
0.7
0.7
0.9
IB33S
3.3 V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger
0.6
0.8
ns
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP=2.3 V for delays.
5. All –F parts are only available as commercial.
Table 1-34 • Worst-Case Commercial Conditions
VDDP = 2.3 V, VDD = 2.3 V, TJ = 70°C
1
2
Max. tINYH
Max. tINYL
Macro Type
Description
Std.
0.9
–F
Std.
0.6
–F
0.8
1.1
Units
ns
IB25LP
2.5 V, CMOS Input Levels3, Low Power
1.1
0.9
IB25LPS
Notes:
2.5 V, CMOS Input Levels3, Low Power, Schmitt Trigger
0.7
0.9
ns
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP=2.3 V for delays.
5. All –F parts are only available as commercial.
1-46
v5.2
ACTEL [ Actel Corporation ]
