PLUS
ProASIC
Flash Family FPGAs
Table 1-39 • Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
1
2
Max. tINYH
Max. tINYL
Std.
Macro Type
GL33
Description
3.3V, CMOS Input Levels3, No Pull-up Resistor
3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger
PPECL Input Levels
Std.
1.1
1.1
GL33S
1.1
1.1
PECL
1.1
1.1
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP=2.3V for delays.
Table 1-40 • Worst-Case Military Conditions
VDDP = 2.3V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
1
2
Max. tINYH
Std.
Max. tINYL
Std.
Macro Type
Description
2.5V, CMOS Input Levels3, Low Power
2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger
GL25LP
GL25LPS
Notes:
1.0
1.1
1.4
1.0
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP=2.3V for delays.
v5.2
1-49
ACTEL [ Actel Corporation ]
