PLUS
ProASIC
Flash Family FPGAs
Output Buffer Delays
A
50%
50%
VOH
PAD
A
50%
PAD
VOL
50%
35pF
OBx
tDLH
tDHL
Figure 1-27 • Output Buffer Delays
Table 1-29 • Worst-Case Commercial Conditions
VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70°C
1
2
Max tDLH
Max tDHL
Macro Type
OB33PH
OB33PN
OB33PL
Description
3.3 V, PCI Output Current, High Slew Rate
3.3 V, High Output Current, Nominal Slew Rate
3.3 V, High Output Current, Low Slew Rate
3.3 V, Low Output Current, High Slew Rate
3.3 V, Low Output Current, Nominal Slew Rate
3.3 V, Low Output Current, Low Slew Rate
Std.
–F
Std.
2.2
2.9
3.2
4.0
4.3
5.6
–F
2.6
3.5
3.9
4.8
5.2
6.7
Units
ns
2.0
2.2
2.5
2.6
2.9
3.0
2.4
2.6
3.0
3.1
3.5
3.6
ns
ns
OB33LH
OB33LN
OB33LL
ns
ns
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. All –F parts are only available as commercial.
Table 1-30 • Worst-Case Commercial Conditions
VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70°C
1
2
Max tDLH
Max tDHL
Macro Type
Description
Std.
2.0
2.4
2.9
2.7
3.5
4.0
–F
Std.
2.1
3.0
3.2
4.6
4.2
5.3
–F
2.6
3.6
3.8
5.5
5.1
6.4
Units
ns
OB25LPHH
OB25LPHN
OB25LPHL
OB25LPLH
OB25LPLN
OB25LPLL
Notes:
2.5 V, Low Power, High Output Current, High Slew Rate3
2.4
2.9
3.5
3.3
4.2
4.8
2.5 V, Low Power, High Output Current, Nominal Slew Rate3
2.5 V, Low Power, High Output Current, Low Slew Rate3
2.5 V, Low Power, Low Output Current, High Slew Rate3
2.5 V, Low Power, Low Output Current, Nominal Slew Rate3
2.5 V, Low Power, Low Output Current, Low Slew Rate3
ns
ns
ns
ns
ns
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. Low-power I/Os work with VDDP=2.5 V 10% only. VDDP=2.3 V for delays.
4. All –F parts are only available as commercial.
1-44
v5.2
ACTEL [ Actel Corporation ]
