PLUS
ProASIC
Flash Family FPGAs
Predicted Global Routing Delay
Table 1-41 • Worst-Case Commercial Conditions1
VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C
Max.
Parameter
tRCKH
Description
Std.
1.1
1.0
0.8
0.8
–F2
1.3
1.2
1.0
1.0
Units
ns
Input Low to High3
Input High to Low3
Input Low to High4
Input High to Low4
tRCKL
ns
tRCKH
ns
tRCKL
ns
Notes:
1. The timing delay difference between tile locations is less than 15ps.
2. All –F parts are only available as commercial.
3. Highly loaded row 50%.
4. Minimally loaded row.
Table 1-42 • Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
Parameter
tRCKH
Description
Max.
Units
Input Low to High (high loaded row of 50ꢀ)
Input High to Low (high loaded row of 50ꢀ)
Input Low to High (minimally loaded row)
Input High to Low (minimally loaded row)
1.1
1.0
0.8
0.8
ns
ns
ns
ns
tRCKL
tRCKH
tRCKL
Note: * The timing delay difference between tile locations is less than 15 ps.
Global Routing Skew
Table 1-43 • Worst-Case Commercial Conditions
VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C
Max.
Parameter
tRCKSWH
Description
Maximum Skew Low to High
Maximum Skew High to Low
Std.
270
270
–F*
320
320
Units
ps
tRCKSHH
ps
Note: *All –F parts are only available as commercial.
Table 1-44 • Worst-Case Commercial Conditions
V
DDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
Description
Maximum Skew Low to High
Maximum Skew High to Low
Parameter
tRCKSWH
Max.
Units
ps
270
270
tRCKSHH
ps
1-50
v5.2
ACTEL [ Actel Corporation ]
