PLUS
ProASIC
Flash Family FPGAs
Table 1-46 • Recommended Operating Conditions
Limits
Parameter
Symbol
fCLOCK
fRAM
Commercial/Industrial
180 MHz
Military/MIL-STD-883
180 MHz
Maximum Clock Frequency*
Maximum RAM Frequency*
Maximum Rise/Fall Time on Inputs*
150 MHz
150 MHz
•
•
Schmitt Trigger Mode (10ꢀ to 90ꢀ)
tR/tF
tR/tF
N/A
100 ns
10 ns
Non-Schmitt Trigger Mode (10ꢀ to
90ꢀ)
100 ns
Maximum LVPECL Frequency*
Maximum TCK Frequency (JTAG)
180 MHz
10 MHz
180 MHz
10 MHz
fTCK
Note: *All –F parts will be 20% slower than standard commercial devices.
Table 1-47 • Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25°C
Type
Trig. Level Rising Edge (ns) Slew Rate (V/ns) Falling Edge (ns) Slew Rate (V/ns)
PCI Mode
Yes
No
OB33PH
OB33PN
OB33PL
OB33LH
OB33LN
OB33LL
10ꢀ-90ꢀ
10ꢀ-90ꢀ
10ꢀ-90ꢀ
10ꢀ-90ꢀ
10ꢀ-90ꢀ
10ꢀ-90ꢀ
1.60
1.57
1.57
3.80
4.19
5.49
1.55
1.70
1.97
3.57
4.65
5.52
1.65
1.68
1.68
0.70
0.63
0.48
1.29
1.18
1.02
0.56
0.43
0.36
1.65
3.32
1.99
4.84
3.37
2.98
1.56
2.08
2.09
3.93
3.28
3.44
1.60
0.80
1.32
0.55
0.78
0.89
1.28
0.96
0.96
0.51
0.61
0.58
No
No
No
No
OB25LPHH 10ꢀ-90ꢀ
OB25LPHN 10ꢀ-90ꢀ
No
No
OB25LPHL
OB25LPLH
OB25LPLN
OB25LPLL
Notes:
10ꢀ-90ꢀ
10ꢀ-90ꢀ
10ꢀ-90ꢀ
10ꢀ-90ꢀ
No
No
No
No
1. Standard and –F parts.
2. All –F only available as commercial.
1-52
v5.2
ACTEL [ Actel Corporation ]
