PLUS
ProASIC
Flash Family FPGAs
Table 1-27 • Worst-Case Military Conditions
VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 125°C for Military/MIL-STD-883
Max
Max
Max
tENZH
Max
1
2
3
4
tDLH
Std.
2.2
tDHL
Std.
2.4
tENZL
Std.
2.1
Macro Type
OTB33PH
OTB33PN
OTB33PL
OTB33LH
OTB33LN
OTB33LL
Notes:
Description
Std.
2.3
2.7
2.9
3.0
3.4
3.5
Units
ns
3.3 V, PCI Output Current, High Slew Rate
3.3 V, High Output Current, Nominal Slew Rate
3.3 V, High Output Current, Low Slew Rate
3.3 V, Low Output Current, High Slew Rate
3.3 V, Low Output Current, Nominal Slew Rate
3.3 V, Low Output Current, Low Slew Rate
2.4
3.2
2.3
ns
2.7
3.5
3.0
ns
2.7
4.3
3.1
ns
3.3
4.7
4.4
ns
3.2
6.0
5.9
ns
1. tDLH=Data-to-Pad High
2. tDHL=Data-to-Pad Low
3. tENZH=Enable-to-Pad, Z to High
4. tENZL = Enable-to-Pad, Z to Low
Table 1-28 • Worst-Case Military Conditions
VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 125°C for Military/MIL-STD-883
Max
tDLH
Max
Max
Max
1
2
3
4
tDHL
Std.
2.3
tENZH
Std.
2.4
tENZL
Std.
2.1
Macro Type
OTB25LPHH
OTB25LPHN
Description
Std.
2.3
Units
ns
2.5 V, Low Power, High Output Current, High Slew Rate5
2.5 V, Low Power, High Output Current, Nominal Slew
Rate5
2.7
3.2
2.8
2.1
ns
OTB25LPHL
OTB25LPLH
OTB25LPLN
OTB25LPLL
Notes:
2.5 V, Low Power, High Output Current, Low Slew Rate5
2.5 V, Low Power, Low Output Current, High Slew Rate5
2.5 V, Low Power, Low Output Current, Nominal Slew Rate5
2.5 V, Low Power, Low Output Current, Low Slew Rate5
3.2
3.0
3.7
4.4
3.5
5.0
4.5
5.8
3.3
3.2
4.1
4.4
2.8
2.8
4.1
5.4
ns
ns
ns
ns
1. tDLH=Data-to-Pad High
2. tDHL=Data-to-Pad Low
3. tENZH=Enable-to-Pad, Z to High
4. tENZL = Enable-to-Pad, Z to Low
5. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays.
v5.2
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