PLUS
ProASIC
Flash Family FPGAs
Table 1-24 • AC Specifications (3.3 V PCI Revision 2.2 Operation)
Commercial/Industrial/Military/MIL-STD- 883
Symbol Parameter
Condition
Min.
–12VDDP
Max.
Units
mA
*
IOH(AC) Switching Current High 0 < VOUT ≤ 0.3VDDP
*
0.3VDDP ≤ VOUT < 0.9VDDP
(–17.1 + (VDDP – VOUT))
mA
*
0.7VDDP < VOUT < VDDP
See equation C – page 124 of
the PCI Specification
document rev. 2.2
*
(Test Point)
VOUT = 0.7VDDP
–32VDDP
mA
mA
mA
*
IOL(AC)
Switching Current Low VDDP > VOUT ≥ 0.6VDDP
16VDDP
1
0.6VDDP > VOUT > 0.1VDDP
(26.7VOUT
)
0.18VDDP > VOUT > 0*
See equation D – page 124 of
the PCI Specification
document rev. 2.2
(Test Point)
VOUT = 0.18VDDP
38VDDP
mA
mA
ICL
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
ICH
VDDP + 4 > VIN ≥ VDDP + 1
0.2VDDP to 0.6VDDP load*
0.6VDDP to 0.2VDDP load*
25 + (VIN – VDDP – 1)/0.015
mA
slewR
slewF
1
1
4
4
V/ns
V/ns
Note: * Refer to the PCI Specification document rev. 2.2.
Pad Loading Applicable to the Rising Edge PCI
pin
1/2 in. max
output
buffer
10 pF
1kΩ
Pad Loading Applicable to the Falling Edge PCI
pin
1kΩ
output
buffer
10 pF
v5.2
1-41
ACTEL [ Actel Corporation ]
