PLUS
ProASIC
Flash Family FPGAs
Table 1-23 • DC Specifications (3.3 V PCI Operation)1
Commercial/
Industrial2,3
Military/MIL-STD- 8832,3
Symbol Parameter
Condition
Min.
2.3
Max.
2.7
Min.
2.3
Max.
2.7
Units
V
VDD
VDDP
VIH
VIL
Supply Voltage for Core
Supply Voltage for I/O Ring
Input High Voltage
3.0
3.6
3.0
3.6
V
0.5VDDP VDDP + 0.5
0.5VDDP
–0.5
VDDP + 0.5
0.3VDDP
V
Input Low Voltage
–0.5
0.7VDDP
–10
0.3VDDP
V
IIPU
IIL
Input Pull-up Voltage4
Input Leakage Current5
0.7VDDP
–50
V
0 < VIN < VDDP
Std.
10
50
µA
µA
V
–F3, 6
–10
100
VOH
Output High Voltage
IOUT = –500 µA
IOUT = 1500 µA
0.9VDDP
0.9VDDP
VOL
Output Low Voltage
0.1VDDP
10
0.1VDDP
10
V
CIN
Input Pin Capacitance (except CLK)
CLK Pin Capacitance
pF
pF
CCLK
Notes:
5
12
5
12
1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only.
2. All process conditions. Junction Temperature: –40 to +110°C for Commercial and Industrial devices and –55 to +125°C for Military.
3. All –F parts are available as commercial only.
4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum
current at this input voltage.
5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.
1-40
v5.2
ACTEL [ Actel Corporation ]
