PLUS
ProASIC
Flash Family FPGAs
Related Documents
Application Notes
Efficient Use of ProASIC Clock Trees
http://www.actel.com/documents/A500K_Clocktree_AN.pdf
I/O Features in ProASICPLUS Flash FPGAs
http://www.actel.com/documents/APA_LVPECL_AN.pdf
Power-Up Behavior of ProASICPLUS Devices
http://www.actel.com/documents/APA_PowerUp.pdf
ProASICPLUS PLL Dynamic Reconfiguration Using JTAG
http://www.actel.com/documents/APA_PLLdynamic_AN.pdf
Using ProASICPLUS Clock Conditioning Circuits
http://www.actel.com/documents/APA_PLL_AN.pdf
In-System Programming ProASICPLUS Devices
http://www.actel.com/documents/APA_External_ISP_AN.pdf
Performing Internal In-System Programming Using Actel’s ProASICPLUS Devices
http://www.actel.com/documents/APA_Microprocessor_AN.pdf
ProASICPLUS RAM and FIFO Blocks
http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf
White Paper
Design Security in Nonvolatile Flash and Antifuse FPGAs
http://www.actel.com/documents/DesignSecurity_WP.pdf
User’s Guide
Designer User’s Guide
http://www.actel.com/documents/designer_UG.pdf
ACTgen User’s Guide
http://www.actel.com/documents/genguide_UG.pdf
ProASIC and ProASICPLUS Macro Library Guide
http://www.actel.com/documents/pa_libguide_UG.pdf
Additional Information
The following link contains additional information on ProASICPLUS Devices.
http://www.actel.com/products/proasicplus/info.aspx
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ACTEL [ Actel Corporation ]
