PLUS
ProASIC
Flash Family FPGAs
DI <0:8>
WADDR <0:7>
DO <0:8>
RADDR <0:7>
DO <0:8>
RADDR <0:7>
DI <0:8>
WADDR <0:7>
SRAM
(256x9)
SRAM
(256x9)
WRB
WBLKB
RDB
RBLKB
RCLKS
RDB
RBLKB
RCLKS
WRB
Sync Write
and
Sync Read
Ports
Async Write
and
Async Read
Ports
WCLKS
WBLKB
WPE
RPE
RPE
WPE
PARODD
PARODD
DI <0:8>
WADDR <0:7>
DO <0:8>
RADDR <0:7>
DI <0:8>
WADDR <0:7>
DO <0:8>
RADDR <0:7>
SRAM
(256x9)
SRAM
(256x9)
WRB
WBLKB
WRB
WBLKB
RDB
RBLKB
RDB
RBLKB
Sync Write
and
Async Read
Ports
Async Write
and
Sync Read
Ports
WCLKS
WPE
RCLKS
RPE
RPE
WPE
PARODD
PARODD
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
Figure 1-21 • Example SRAM Block Diagrams
Table 1-13 • Memory Block SRAM Interface Signals
Description
Write clock used on synchronization on write side
Read clock used on synchronization on read side
Read address
SRAM Signal
WCLKS
RCLKS
Bits
1
In/Out
In
1
In
RADDR<0:7>
RBLKB
8
In
1
In
Read block select (active Low)
RDB
1
In
Read pulse (active Low)
WADDR<0:7>
WBLKB
8
In
Write address
1
In
Write block select (active Low)
DI<0:8>
WRB
9
In
Input data bits <0:8>, <8> can be used for parity In
Write pulse (active Low)
1
In
DO<0:8>
RPE
9
Out
Out
Out
In
Output data bits <0:8>, <8> can be used for parity Out
Read parity error (active High)
1
WPE
1
Write parity error (active High)
PARODD
1
Selects Odd parity generation/detect when High, Even parity when Low
Note: Not all signals shown are used in all modes.
1-24
v5.2
ACTEL [ Actel Corporation ]
