PLUS
ProASIC
Flash Family FPGAs
DI<0:8>
LEVEL<0:7>
LGDEP<0:2>
DI<0:8>
LEVEL<0:7>
LGDEP<0:2>
DO <0:8>
DO <0:8>
WPE
FIFO
(256x9)
FIFO
(256x9)
WPE
RPE
WRB
WBLKB
WRB
WBLKB
RPE
FULL
EMPTY
FULL
EMPTY
Sync Write
and
Sync Read
Ports
Sync Write
and
Async Read
Ports
RDB
RBLKB
RDB
RBLKB
EQTH
EQTH
PARODD
PARODD
GEQTH
GEQTH
WCLKS
WCLKS
RESET
RCLKS
RESET
DI <0:8>
LEVEL <0:7>
LGDEP<0:2>
DI <0:8>
LEVEL <0:7>
LGDEP<0:2>
DO <0:8>
WPE
DO <0:8>
FIFO
(256x9)
FIFO
(256x9)
WRB
WBLKB
WRB
WBLKB
WPE
RPE
RPE
FULL
FULL
EMPTY
Async Write
and
Sync Read
Ports
Async Write
and
Async Read
Ports
RDB
RBLKB
EMPTY
EQTH
EQTH
RDB
PARODD
RBLKB
GEQTH
RESET
RCLKS
GEQTH
PARODD
RESET
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
Figure 1-22 • Basic FIFO Block Diagrams
Table 1-14 • Memory Block FIFO Interface Signals
FIFO Signal
WCLKS
Bits
1
In/Out
In
Description
Write clock used for synchronization on write side
Read clock used for synchronization on read side
Direct configuration implements static flag logic
Read block select (active Low)
RCLKS
1
In
LEVEL <0:7>
RBLKB
8
In
1
In
RDB
1
In
Read pulse (active Low)
RESET
1
In
Reset for FIFO pointers (active Low)
WBLKB
1
In
Write block select (active Low)
DI<0:8>
WRB
9
In
Input data bits <0:8>, <8> will be generated parity if PARGEN is true
Write pulse (active Low)
1
In
FULL, EMPTY
EQTH, GEQTH
2
Out
Out
FIFO flags. FULL prevents write and EMPTY prevents read
2
EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.
GEQTH is true when the FIFO holds (LEVEL) words or more
DO<0:8>
RPE
9
1
1
3
1
Out
Out
Out
In
Output data bits <0:8>. <8> will be parity output if PARGEN is true.
Read parity error (active High)
WPE
Write parity error (active High)
Configures DEPTH of the FIFO to 2 (LGDEP+1)
LGDEP <0:2>
PARODD
In
Parity generation/detect – Even when Low, Odd when High
v5.2
1-25
ACTEL [ Actel Corporation ]
