PLUS
ProASIC
Flash Family FPGAs
The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles.
This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as
follows:
P
clock
Fs
=
=
10 MHz
13,440
R
=> Pclock = (P1 + (P2*R) - (P7*R2)) * Fs = 121.5 mW
P
storage
ms
= 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)
=> Pstorage = P5 * ms * Fs = 147.8 mW
P
logic
mc = 0 (no logic tiles in this shift register)
=> Plogic = 0 mW
P
outputs
Cload
=
=
=
=
40 pF
3.3 V
24
VDDP
p
Fp
5 MHz
=> Poutputs = (P4 + (Cload * VDDP2)) * p * Fp = 91.4 mW
P
inputs
q
=
=
1
Fq
10 MHz
=> Pinputs = P8 * q * Fq = 0.3 mW
P
memory
Nmemory
=
0 (no RAM/FIFO blocks in this shift register)
=> Pmemory = 0 mW
Pac
=> 361 mW
Ptotal
Pdc + Pac = 374 mW (typical)
1-32
v5.2
ACTEL [ Actel Corporation ]
