PLUS
ProASIC
Flash Family FPGAs
9
Word Width
9
9
9
9
256
9
256
256
9
256
256
9
256
9
256
256
Word
Depth
256
88 blocks
Figure 1-23 • APA1000 Memory Block Architecture
Word Width
9
9
9
9
9
Word
256
256 256
256 256
256 256
Depth
256 words x 18 bits, 1 read, 1 write
256
512 words x 18 bits, 1 read, 1 write
256
256
1,024 words x 9 bits, 1 read, 1 write
Total Memory Blocks Used = 10
Total Memory Bits = 23,040
Figure 1-24 • Example Showing Memory Arrays with Different Widths and Depths
Word Width
9
9
9
Write Port
Write Port
9
9
99
9
9
Word
Depth
256 256
256 256 256 256
256 256 256 256
Read Ports
256 words x 9 bits, 2 read, 1 write
Read Ports
512 words x 9 bits, 4 read, 1 write
Total Memory Blocks Used = 10
Total Memory Bits = 6,912
Figure 1-25 • Multi-Port Memory Usage
1-26
v5.2
ACTEL [ Actel Corporation ]
