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AFS600-2FGG256I 参数 Datasheet PDF下载

AFS600-2FGG256I图片预览
型号: AFS600-2FGG256I
PDF下载: 下载PDF文件 查看货源
内容描述: Actel的Fusion混合信号FPGA [Actel Fusion Mixed-Signal FPGAs]
分类和应用:
文件页数/大小: 318 页 / 10484 K
品牌: ACTEL [ Actel Corporation ]
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Actel Fusion Mixed-Signal FPGAs  
ADC Input Multiplexer  
At the input to the Fusion ADC is a 32:1 multiplexer. Of the 32 input channels, up to 30 are user  
definable. Two of these channels are hardwired internally. Channel 31 connects to an internal  
temperature diode so the temperature of the Fusion device itself can be monitored. Channel 0 is  
wired to the FPGA’s 1.5 V VCC supply, enabling the Fusion device to monitor its own power supply.  
Doing this internally makes it unnecessary to use an analog I/O to support these functions. The  
balance of the MUX inputs are connected to Analog Quads (see the "Analog Quad" section on  
page 2-84). Table 2-39 defines which Analog Quad inputs are associated with which specific analog  
MUX channels. The number of Analog Quads present is device-dependent; refer to the family list in  
the "Fusion Family" table on page I of this datasheet for the number of quads per device.  
Regardless of the number of quads populated in a device, the internal connections to both VCC and  
the internal temperature diode remain on Channels 0 and 31, respectively. To sample the internal  
temperature monitor, it must be strobed (similar to the AT pads). The TMSTBINT pin on the Analog  
Block macro is the control for strobing the internal temperature measurement diode.  
To determine which channel is selected for conversion, there is a five-pin interface on the Analog  
Block, CHNUMBER[4:0], defined in Table 2-40 on page 2-102. Table 2-39 shows the correlation  
between the analog MUX input channels and the analog input pins.  
Table 2-39 • Analog MUX Channels  
Analog MUX Channel  
Signal  
Vcc_analog  
AV0  
AC0  
Analog Quad Number  
0
1
Analog Quad 0  
2
3
AT0  
4
AV1  
AC1  
Analog Quad 1  
Analog Quad 2  
Analog Quad 3  
Analog Quad 4  
Analog Quad 5  
Analog Quad 6  
5
6
AT1  
7
AV2  
AC2  
8
9
AT2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
AV3  
AC3  
AT3  
AV4  
AC4  
AT4  
AV5  
AC5  
AT5  
AV6  
AC6  
AT6  
Preliminary v1.7  
2-101  
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