HiRel FPGAs
A1280XL Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
Min. Max.
‘Std’ Speed
Min. Max.
Parameter
Description
Units
TTL Output Module Timing1
tDLH
Data to Pad High
5.3
5.7
6.2
ns
ns
tDHL
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
6.6
6.2
tENZH
tENZL
tENHZ
tENLZ
tGLH
5.3
ns
5.8
6.8
ns
7.5
8.9
ns
7.5
8.9
ns
5.9
6.9
ns
tGHL
G to Pad Low
6.6
7.8
ns
dTLH
dTHL
Delta Low to High
0.05
0.05
0.06
0.09
ns/pF
ns/pF
Delta High to Low
CMOS Output Module Timing1
tDLH
Data to Pad High
6.6
4.7
7.9
5.5
ns
ns
tDHL
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
tENZH
tENZL
tENHZ
tENLZ
tGLH
5.3
6.2
ns
5.8
6.8
ns
7.5
8.9
ns
7.5
8.9
ns
5.9
6.9
ns
tGHL
G to Pad Low
6.6
7.8
ns
dTLH
dTHL
Notes:
Delta Low to High
Delta High to Low
0.07
0.06
0.09
0.09
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
35
ACTEL [ Actel Corporation ]
