欢迎访问ic37.com |
会员登录 免费注册
发布采购

A32100DX-CQ84B 参数 Datasheet PDF下载

A32100DX-CQ84B图片预览
型号: A32100DX-CQ84B
PDF下载: 下载PDF文件 查看货源
内容描述: HiRel它的FPGA [HiRel FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 98 页 / 2009 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A32100DX-CQ84B的Datasheet PDF文件第32页浏览型号A32100DX-CQ84B的Datasheet PDF文件第33页浏览型号A32100DX-CQ84B的Datasheet PDF文件第34页浏览型号A32100DX-CQ84B的Datasheet PDF文件第35页浏览型号A32100DX-CQ84B的Datasheet PDF文件第37页浏览型号A32100DX-CQ84B的Datasheet PDF文件第38页浏览型号A32100DX-CQ84B的Datasheet PDF文件第39页浏览型号A32100DX-CQ84B的Datasheet PDF文件第40页  
A1425A Timing Characteristics  
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)  
‘–1’ Speed  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Units  
Logic Module Propagation Delays1  
tPD  
Internal Array Module  
Sequential Clock to Q  
Asynchronous Clear to Q  
3.0  
3.0  
3.0  
3.5  
3.5  
3.5  
ns  
ns  
ns  
tCO  
tCLR  
Logic Module Predicted Routing Delays2  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
1.3  
1.9  
2.1  
2.6  
4.2  
1.5  
2.1  
2.5  
2.9  
4.9  
ns  
ns  
ns  
ns  
ns  
Logic Module Sequential Timing  
tSUD  
Flip-Flop (Latch) Data Input Setup  
0.9  
0.0  
0.9  
0.0  
3.8  
3.8  
7.9  
1.0  
0.0  
1.0  
0.0  
4.4  
4.4  
9.3  
ns  
ns  
tHD  
Flip-Flop (Latch) Data Input Hold  
Flip-Flop (Latch) Enable Setup  
Flip-Flop (Latch) Enable Hold  
Asynchronous Pulse Width  
Flip-Flop Clock Pulse Width  
Flip-Flop Clock Input Period  
Flip-Flop Clock Frequency  
tSUENA  
tHENA  
tWASYN  
tWCLKA  
tA  
ns  
ns  
ns  
ns  
ns  
fMAX  
125  
100  
MHz  
Input Module Propagation Delays  
tINY  
Input Data Pad to Y  
4.2  
7.0  
7.0  
7.0  
7.0  
4.9  
8.2  
8.2  
8.2  
8.2  
ns  
ns  
ns  
ns  
ns  
tICKY  
Input Reg IOCLK Pad to Y  
Output Reg IOCLK Pad to Y  
Input Asynchronous Clear to Y  
Output Asynchronous Clear to Y  
tOCKY  
tICLRY  
tOCLRY  
Input Module Predicted Routing Delays1, 3  
tIRD1  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
Notes:  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
1.3  
1.9  
2.1  
2.6  
4.2  
1.5  
2.1  
2.5  
2.9  
4.9  
ns  
ns  
ns  
ns  
ns  
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is  
based on actual routing delay measurements performed on the device prior to shipment.  
3. Optimization techniques may further reduce delays by 0 to 4 ns.  
36  
 复制成功!