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A32100DX-CQ84B 参数 Datasheet PDF下载

A32100DX-CQ84B图片预览
型号: A32100DX-CQ84B
PDF下载: 下载PDF文件 查看货源
内容描述: HiRel它的FPGA [HiRel FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 98 页 / 2009 K
品牌: ACTEL [ Actel Corporation ]
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A1425A Timing Characteristics (continued)  
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)  
‘–1’ Speed  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Units  
CMOS Output Module Timing1  
tDHS  
Data to Pad, High Slew  
9.2  
10.8  
20.3  
9.1  
ns  
ns  
tDLS  
Data to Pad, Low Slew  
17.3  
7.7  
tENZHS  
tENZLS  
tENHSZ  
tENLSZ  
tCKHS  
tCKLS  
Enable to Pad, Z to H/L, High Slew  
Enable to Pad, Z to H/L, Low Slew  
Enable to Pad, H/L to Z, High Slew  
Enable to Pad, H/L to Z, Low Slew  
IOCLK Pad to Pad H/L, High Slew  
IOCLK Pad to Pad H/L, Low Slew  
Delta Low to High, High Slew  
Delta Low to High, Low Slew  
Delta High to Low, High Slew  
Delta High to Low, Low Slew  
ns  
13.1  
9.9  
15.5  
11.6  
11.6  
13.7  
20.1  
0.07  
0.13  
0.05  
0.06  
ns  
ns  
10.5  
12.5  
18.1  
0.06  
0.11  
0.04  
0.05  
ns  
ns  
ns  
dTLHHS  
dTLHLS  
dTHLHS  
dTHLLS  
ns/pF  
ns/pF  
ns/pF  
ns/pF  
Dedicated (Hard-Wired) I/O Clock Network  
tIOCKH  
Input Low to High  
(Pad to I/O Module Input)  
3.0  
3.5  
ns  
ns  
tIOPWH  
tIOPWL  
tIOSAPW  
tIOCKSW  
tIOP  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Minimum Asynchronous Pulse Width  
Maximum Skew  
3.9  
3.9  
3.9  
4.4  
4.4  
4.4  
ns  
ns  
0.5  
0.5  
ns  
Minimum Period  
7.9  
9.3  
ns  
fIOMAX  
Maximum Frequency  
125  
100  
MHz  
Dedicated (Hard-Wired) Array Clock Network  
tHCKH  
Input Low to High  
(Pad to S-Module Input)  
4.6  
4.6  
5.3  
5.3  
ns  
tHCKL  
Input High to Low  
(Pad to S-Module Input)  
ns  
ns  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Maximum Skew  
3.9  
3.9  
4.4  
4.4  
ns  
0.4  
0.4  
ns  
Minimum Period  
7.9  
9.3  
ns  
fHMAX  
Notes:  
Maximum Frequency  
125  
100  
MHz  
1. Delays based on 35 pF loading.  
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at  
http://www.actel.com/appnotes.  
38  
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