HiRel FPGAs
A1280A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
4.0
3.6
6.9
6.6
4.7
ns
ns
ns
ns
4.3
8.1
7.7
Input Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
6.2
7.2
7.3
8.4
ns
ns
ns
ns
ns
7.7
9.1
8.9
10.5
15.2
12.9
Global Clock Network
tCKH Input Low to High
FO = 32
FO = 384
13.3
17.9
15.7
21.1
ns
ns
tCKL
Input High to Low
FO = 32
FO = 384
13.3
18.2
15.7
21.4
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
FO = 32
FO = 384
0.6
3.1
0.6
3.1
ns
Input Latch External Setup
Input Latch External Hold
Minimum Period
FO = 32
FO = 384
0.0
0.0
0.0
0.0
ns
FO = 32
FO = 384
8.6
13.8
8.6
13.8
ns
FO = 32
FO = 384
13.7
16.0
16.2
18.9
ns
fMAX
Note:
Maximum Frequency
FO = 32
FO = 384
73
63
62
53
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
31
ACTEL [ Actel Corporation ]
