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A32100DX-CQ84B 参数 Datasheet PDF下载

A32100DX-CQ84B图片预览
型号: A32100DX-CQ84B
PDF下载: 下载PDF文件 查看货源
内容描述: HiRel它的FPGA [HiRel FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 98 页 / 2009 K
品牌: ACTEL [ Actel Corporation ]
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A1280XL Timing Characteristics (continued)  
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)  
‘–1’ Speed  
‘Std’ Speed  
Parameter Description  
Min.  
Max.  
Min.  
Max.  
Units  
Input Module Propagation Delays  
tINYH  
tINYL  
tINGH  
tINGL  
Pad to Y High  
Pad to Y Low  
G to Y High  
G to Y Low  
1.5  
1.7  
2.8  
3.7  
1.7  
2.1  
3.3  
4.3  
ns  
ns  
ns  
ns  
Input Module Predicted Routing Delays1  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
4.6  
5.2  
5.5  
6.4  
9.2  
5.3  
6.1  
ns  
ns  
ns  
ns  
ns  
6.5  
7.5  
10.8  
Global Clock Network  
tCKH Input Low to High  
FO = 32  
FO = 384  
7.1  
8.0  
8.4  
9.5  
ns  
ns  
tCKL  
Input High to Low  
FO = 32  
FO = 384  
7.0  
8.0  
8.3  
9.5  
tPWH  
tPWL  
tCKSW  
tSUEXT  
tHEXT  
tP  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Maximum Skew  
FO = 32  
FO = 384  
4.3  
4.8  
5.3  
5.7  
ns  
FO = 32  
FO = 384  
4.3  
4.8  
5.3  
5.7  
ns  
FO = 32  
FO = 384  
1.1  
1.1  
1.2  
1.2  
ns  
Input Latch External Setup  
Input Latch External Hold  
Minimum Period  
FO = 32  
FO = 384  
0.0  
0.0  
0.0  
0.0  
ns  
FO = 32  
FO = 384  
3.6  
4.6  
4.2  
5.3  
ns  
FO = 32  
FO = 384  
9.1  
9.8  
10.7  
11.8  
ns  
fMAX  
Note:  
Maximum Frequency  
FO = 32  
FO = 384  
110  
100  
90  
85  
MHz  
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based  
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0  
to 4 ns.  
34  
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