HiRel FPGAs
A1425A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRP
Input Low to High (FO=64)
5.5
6.0
6.4
7.0
ns
ns
Input High to Low (FO=64)
Min. Pulse Width High (FO=64)
Min. Pulse Width Low (FO=64)
Maximum Skew (FO=128)
Minimum Period (FO=64)
4.9
4.9
5.7
5.7
ns
ns
1.1
1.2
85
ns
10.1
11.6
ns
fRMAX
Maximum Frequency (FO=64)
100
MHz
Clock-to-Clock Skews
tIOHCKSW
tIORCKSW
tHRCKSW
I/O Clock to H-Clock Skew
0.0
0.0
3.0
3.0
0.0
0.0
3.0
3.0
ns
ns
I/O Clock to R-Clock Skew
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
39
ACTEL [ Actel Corporation ]
