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5962-0421901QUA 参数 Datasheet PDF下载

5962-0421901QUA图片预览
型号: 5962-0421901QUA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 250000 Gates, CMOS, CPGA624, CERAMIC, CGA-624]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX A  
A.4.3.2.3 Nondestructive tests. The following tests are classified as nondestructive:  
Barometric pressure  
** Steady-state life  
** Intermittent life  
*** Solderability (for lead finish A only)  
Seal  
External visual  
Internal visual (pre-cap)  
** Burn-in screen  
Radiography  
Particle impact noise detection (PIND)  
Physical dimensions  
Nondestructive 100 percent bond pull test where stress does not exceed the specified pull force and  
positive tolerance  
Resistance to solvents  
C-SAM (TM 2030)  
** When the test temperature exceeds the maximum specified junction temperature for the device (including  
maximum specified for operation or test), these tests may be considered destructive. To ship these tested  
devices, the manufacturer shall have data to support that the test is not destructive and has not degraded the  
device.  
*** For glass sealed devices, lead finish A shall be considered nondestructive unless electrical test, visual inspection,  
or other evaluation shows that package integrity or electrical performance has been degraded.  
A.4.3.3 Formation of lots. Microcircuits shall be segregated into identifiable production lots as defined in A.3.1.3.6  
as required to meet the production control and inspection requirements of A.4.8. Microcircuits shall be formed into  
inspection lots as defined in A.3.1.3.7 and A.3.1.3.8 as required to meet the quality assurance inspection and test  
requirements of this specification.  
Wafer lot processing, as a homogeneous group (see A.3.1.3.11), shall be accomplished by any of the following  
procedures, providing process schedules and controls are sufficiently maintained to assure identical processing in  
accordance with process instructions of all wafers in the lot:  
a. Batch processing of all wafers in the wafer lot through the same machine process step(s) simultaneously.  
b. Continuous or sequential processing (wafer by wafer or batch portions of wafer lot) of all wafers through the  
same machine or process step(s).  
c. Parallel processing of portions of the wafer lot through multiple machines or process stations on the same  
certified line, provided statistical quality control assures and demonstrates correlation between stations and  
separately processed portions of the wafer lot.  
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