MIL-PRF-38535K
APPENDIX A
A.3.6.9 Marking location and sequence. The certification mark, the PIN, identification codes and ESD identifier
shall be located on the top surface of leadless or leaded chip carriers, pin grid array packages, flat packages, or
dual-in-line configurations and on either the top or the side of cylindrical packages (TO configurations and similar
configurations). When the size of a package is insufficient to allow marking of special process identifiers on the top
surface, the backside of the package may be used for these markings except the ESD identifier, if marked, shall be
marked on the top. Button cap flat packs with less than or equal to 16 leads may have the identifier marked on the
ceramic. Backside marking with conductive or resistive ink shall be prohibited.
A.3.6.9.1 Beryllium oxide package identifier. If a microcircuit package contains beryllium oxide (see A.3.5.1 note),
the part shall be marked with the designation "Be0".
A.3.6.9.2 Electrostatic discharge (ESD) sensitivity identifier. Microcircuits shall be ESD classified in accordance
with A.3.4.1.4, however, ESD classification marking is not required. The manufacturer shall have an option of no
ESD marking, marking a single ESD triangle or marking in accordance with the ESD device classification defined in
test method 3015 of MIL-STD-883. Because it may no longer be possible to determine the ESD classification from
the part marking, the device Discharge Sensitivity Classification shall be as listed in MIL-HDBK-103 or QML-38535.
A.3.6.10 Marking on container. See A.5.2.2 for additional marking requirements.
A.3.6.11 Marking option for controlled storage of class level B. Where microcircuits are subjected to testing and
screening in accordance with some portion of the quality assurance requirements and stored in controlled storage
areas pending receipt of orders requiring conformance to the same or a different level, the inspection lot identification
code shall be placed on the microcircuit package along with the other markings specified in 3.6 sufficient to assure
identification of the material. As an alternative, if the microcircuits are stored together with sufficient data to assure
traceability to processing and inspection records, all markings may be applied after completion of all inspections to
the specified level.
A.3.6.12 Marking option for qualification or quality conformance inspection (QCI). The manufacturer has the option
of marking the entire lot or only the sample devices to be submitted to qualification or groups B, C, and D (and E if
applicable) QCI, as applicable. If the manufacturer exercises the option to mark only the sample devices, the
procedures shall be as follows:
a. The sample devices shall be marked prior to performance of groups B, C, and D (and E if applicable)
qualification or QCIs, as applicable.
b. At the completion of inspection, the marking of the sample devices shall be inspected for conformance with the
requirements of A.3.6.
c. The inspection lot represented by the conforming qualification or quality conformance sample shall then be
marked and any specified visual and mechanical inspection performed.
d. The marking materials and processing applied to the inspection lot shall be to the same specifications as those
used for the inspection sample.
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ACTEL [ Actel Corporation ]
