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AD9512 参数 Datasheet PDF下载

AD9512图片预览
型号: AD9512
PDF下载: 下载PDF文件 查看货源
内容描述: 1.2 GHz的时钟分配IC , 1.6 GHz的输入,分频器,延迟调整,五路输出 [1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs]
分类和应用: 时钟
文件页数/大小: 48 页 / 1007 K
品牌: ABCO [ ABCO ELECTRONICS CO.LTD ]
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AD9512  
SERIAL CONTROL PORT  
The AD9512 serial control port is a flexible, synchronous, serial  
communications port that allows an easy interface with many  
industry-standard microcontrollers and microprocessors. The  
AD9512 serial control port is compatible with most  
not brought high at the end of each write or read cycle (on a  
byte boundary), the last byte is not loaded into the register  
buffer.  
CSB stall high is supported in modes where three or fewer bytes  
of data (plus instruction data) are transferred (W1:W0 must be  
set to 00, 01, or 10, see Table 14). In these modes, CSB can  
temporarily return high on any byte boundary, allowing time  
for the system controller to process the next byte. CSB can go  
high on byte boundaries only and can go high during either  
part (instruction or data) of the transfer. During this period, the  
serial control port state machine enters a wait state until all data  
has been sent. If the system controller decides to abort the  
transfer before all of the data is sent, the state machine must be  
reset by either completing the remaining transfer or by  
synchronous transfer formats, including both the Motorola SPI®  
and Intel® SSR protocols. The serial control port allows  
read/write access to all registers that configure the AD9512.  
Single or multiple byte transfers are supported, as well as MSB  
first or LSB first transfer formats. The AD9512 serial control  
port can be configured for a single bidirectional I/O pin (SDIO  
only) or for two unidirectional I/O pins (SDIO/SDO).  
SERIAL CONTROL PORT PIN DESCRIPTIONS  
SCLK (serial clock) is the serial shift clock. This pin is an input.  
SCLK is used to synchronize serial control port reads and  
writes. Write data bits are registered on the rising edge of this  
clock, and read data bits are registered on the falling edge. This  
pin is internally pulled down by a 30 kΩ resistor to ground.  
returning the CSB low for at least one complete SCLK cycle (but  
less than eight SCLK cycles). Raising the CSB on a nonbyte  
boundary terminates the serial transfer and flushes the buffer.  
In the streaming mode (W1:W0 = 11b), any number of data  
bytes can be transferred in a continuous stream. The register  
address is automatically incremented or decremented (see the  
MSB/LSB First Transfers section). CSB must be raised at the  
end of the last byte to be transferred, thereby ending the stream  
mode.  
SDIO (serial data input/output) is a dual-purpose pin and acts  
as either an input only or as both an input/output. The AD9512  
defaults to two unidirectional pins for I/O, with SDIO used as  
an input and SDO as an output. Alternatively, SDIO can be used  
as a bidirectional I/O pin by writing to the SDO enable register  
at 00h<7> = 1b.  
Communication Cycle—Instruction Plus Data  
SDO (serial data out) is used only in the unidirectional I/O  
mode (00h<7> = 0b, default) as a separate output pin for  
reading back data. The AD9512 defaults to this I/O mode.  
Bidirectional I/O mode (using SDIO as both input and output)  
may be enabled by writing to the SDO enable register at  
00h<7> = 1b.  
There are two parts to a communication cycle with the AD9512.  
The first writes a 16-bit instruction word into the AD9512,  
coincident with the first 16 SCLK rising edges. The instruction  
word provides the AD9512 serial control port with information  
regarding the data transfer, which is the second part of the  
communication cycle. The instruction word defines whether  
the upcoming data transfer is a read or a write, the number of  
bytes in the data transfer, and the starting register address for  
the first byte of the data transfer.  
CSB (chip select bar) is an active low control that gates the read  
and write cycles. When CSB is high, SDO and SDIO are in a  
high impedance state. This pin is internally pulled down by a  
30 kΩ resistor to ground. It should not be left NC or tied low.  
See the Framing a Communication Cycle with CSB section on  
the use of the CSB in a communication cycle.  
Write  
If the instruction word is for a write operation (I15 = 0b), the  
second part is the transfer of data into the serial control port  
buffer of the AD9512. The length of the transfer (1, 2, 3 bytes,  
or streaming mode) is indicated by two bits (W1:W0) in the  
instruction byte. CSB can be raised after each sequence of eight  
bits to stall the bus (except after the last byte, where it ends the  
cycle). When the bus is stalled, the serial transfer resumes when  
CSB is lowered. Stalling on nonbyte boundaries resets the serial  
control port.  
SCLK (PIN 14)  
AD9512  
SDIO (PIN 15)  
SERIAL  
SDO (PIN 16)  
CONTROL  
PORT  
CSB (PIN 17)  
Figure 30. Serial Control Port  
GENERAL OPERATION OF SERIAL CONTROL PORT  
Framing a Communication Cycle with CSB  
Each communication cycle (a write or a read operation) is gated  
by the CSB line. CSB must be brought low to initiate a  
communication cycle. CSB must be brought high at the  
completion of a communication cycle (see Figure 38). If CSB is  
Since data is written into a serial control port buffer area, not  
directly into the AD9512s actual control registers, an additional  
operation is needed to transfer the serial control port buffer  
contents to the actual control registers of the AD9512, thereby  
causing them to take effect. This update command consists of  
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