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AD9512 参数 Datasheet PDF下载

AD9512图片预览
型号: AD9512
PDF下载: 下载PDF文件 查看货源
内容描述: 1.2 GHz的时钟分配IC , 1.6 GHz的输入,分频器,延迟调整,五路输出 [1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs]
分类和应用: 时钟
文件页数/大小: 48 页 / 1007 K
品牌: ABCO [ ABCO ELECTRONICS CO.LTD ]
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AD9512  
slave must provide this same frequency back to the DSYNCB  
input of the slave.  
SINGLE-CHIP SYNCHRONIZATION  
SYNCB—Hardware SYNC  
The AD9512 clocks can be synchronized to each other at any  
time. The outputs of the clocks are forced into a known state  
with respect to each other and then allowed to continue  
clocking from that state in synchronicity. Before a  
synchronization is done, the FUNCTION Pin must be set as the  
input (58h<6:5> = 01b). Synchronization is done by forcing the  
FUNCTION pin low, creating a SYNCB signal and then  
releasing it.  
Multichip synchronization is enabled by writing to  
Register 58h<0> = 1b on the slave AD9512. When this bit  
is set, the STATUS pin becomes the output for the SYNC  
signal. A low signal indicates an in-sync condition, and  
a high indicates an out-of-sync condition.  
Register 58h<1> selects the number of fast clock cycles that are  
the maximum separation of the slow clock edges that are  
considered synchronized. When 58h<1> = 0b (default), the  
slow clock edges must be coincident within 1 to 1.5 high speed  
clock cycles. If the coincidence of the slow clock edges is closer  
than this amount, the SYNC flag stays low. If the coincidence of  
the slow clock edges is greater than this amount, the SYNC flag  
is set high. When Register 58h<1> = 1b, the amount of  
coincidence required is 0.5 fast clock cycles to 1 fast clock  
cycles.  
See the SYNCB: 58h<6:5> = 01b section for a more detailed  
description of what happens when the SYNCB: 58h<6:5> = 01b  
signal is issued.  
Soft SYNC—Register 58h<2>  
A soft SYNC can be issued by means of a bit in  
Register 58h<2>. This soft SYNC works the same as the  
SYNCB, except that the polarity is reversed. A 1 written to this  
bit forces the clock outputs into a known state with respect to  
each other. When a 0 is subsequently written to this bit, the  
clock outputs continue clocking from that state in  
synchronicity.  
Whenever the SYNC flag is set (high), indicating an out-of-sync  
condition, a SYNCB signal applied simultaneously at the  
FUNCTION pins of both AD9512s brings the slow clocks into  
synchronization.  
MULTICHIP SYNCHRONIZATION  
AD9512  
MASTER  
The AD9512 provides a means of synchronizing two or more  
AD9512s. This is not an active synchronization; it requires user  
monitoring and action. The arrangement of two AD9512s to be  
synchronized is shown in Figure 29.  
OUTN  
FAST CLOCK  
<1GHz  
FUNCTION  
OUTM  
SLOW CLOCK  
<250MHz  
(SYNCB)  
F
SYNC  
Synchronization of two or more AD9512s requires a fast clock  
and a slow clock. The fast clock can be up to 1 GHz and can be  
the clock driving the master AD9512 CLK1 input or one of the  
outputs of the master. The fast clock acts as the input to the  
distribution section of the slave AD9512 and is connected to its  
CLK1 input.  
SYNCB  
DSYNC  
DSYNCB  
AD9512  
SLAVE  
SLOW  
CLOCK  
<250MHz  
F
SYNC  
OUTY  
FAST CLOCK  
<1GHz  
SYNC  
DETECT  
CLK1  
The slow clock is the clock that is synchronized across the two  
chips. This clock must be no faster than one-fourth of the fast  
clock, and no greater than 250 MHz. The slow clock is taken  
from one of the outputs of the master AD9512 and acts as a  
DSYNC input to the slave AD9512. One of the outputs of the  
FUNCTION  
(SYNCB)  
SYNCSTATUS  
Figure 29. Multichip Synchronization  
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