AD9512
DIV = 18
This path adds some jitter greater than that specified for the
nondelay outputs. This means that the delay function should be
used primarily for clocking digital chips, such as FPGA, ASIC,
DUC, and DDC, rather than for data converters. The jitter is
higher for long full scales (~10 ns). This is because the delay
block uses a ramp and trip points to create the variable delay. A
longer ramp means more noise might be introduced.
Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14, 15, 16, 17
Phase offsets may be related to degrees by calculating the phase
step for a particular divide ratio:
Phase Step = 360°/(Divide Ratio) = 360°/DIV
Using some of the same examples,
DIV = 4
Calculating the Delay
The following values and equations are used to calculate the
delay of the delay block.
Value of Ramp Current Control Bits (Register 35h or Register 39h
<2:0>) = Iramp_bits
Phase Step = 360°/4 = 90°
Unique Phase Offsets in Degrees Are Phase = 0°, 90°,
180°, 270°
I
RAMP (μA) = 200 × (Iramp_bits + 1)
No. of Caps = No. of 0s + 1 in Ramp Control Capacitor
(Register 35h or Register 39h <5:3>), that is, 101 = 1 + 1 = 2;
110 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1)
DIV = 7
Phase Step = 360°/7 = 51.43°
Delay_Range (ns) = 200 × [(No. of Caps + 3)/(IRAMP)] × 1.3286
Unique Phase Offsets in Degrees Are Phase = 0°, 51.43°,
102.86°, 154.29°, 205.71°, 257.15°, 308.57°
⎛ No.of Caps −1⎞
×10−4
+
×6
⎜
⎜
⎝
⎟
⎟
⎠
Offset
(
ns
)
= 0.34 +
(
1600 − IRAMP
)
DELAY BLOCK
IRAMP
OUT4 (LVDS/CMOS) includes an analog delay element that
can be programmed (Register 34h to Register 36h) to give
variable time delays (ΔT) in the clock signal passing through
that output.
Delay_Full_Scale (ns) = Delay_Range + Offset
Fine_Adj = Value of Delay Fine Adjust (Register 36h or
Register 3Ah <5:1>), that is, 11111 = 31
CLOCK INPUT
OUT4 ONLY
Delay (ns) = Offset + Delay_Range × Fine_adj × (1/31)
OUTPUTS
÷N
∅SELECT
The AD9512 offers three different output level choices:
LVDS
CMOS
LVPECL, LVDS, and CMOS. OUT0 to OUT2 are LVPECL only.
OUT3 and OUT4 can be selected as either LVDS or CMOS.
Each output can be enabled or turned off as needed to save
power.
OUTPUT
DRIVER
ΔT
FINE DELAY ADJUST
(32 STEPS)
FULL-SCALE: 1ns TO 10ns
The simplified equivalent circuit of the LVPECL outputs is
shown in Figure 27.
Figure 26. Analog Delay (OUT4)
The amount of delay that can be used is determined by the
frequency of the clock being delayed. The amount of delay can
approach one-half cycle of the clock period. For example, for a
10 MHz clock, the delay can extend to the full 10 ns maximum
of which the delay element is capable. However, for a 100 MHz
clock (with 50ꢀ duty cycle), the maximum delay is less than
5 ns (or half of the period).
3.3V
OUT
OUTB
OUT4 allows a full-scale delay in the range 1 ns to 10 ns. The
full-scale delay is selected by choosing a combination of ramp
current and the number of capacitors by writing the appropriate
values into Register 35h. There are 32 fine delay settings for
each full scale, set by Register 36h.
GND
Figure 27. LVPECL Output Simplified Equivalent Circuit
Rev. A | Page 30 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
