FEDL87V2107-01
OKI Semiconductor
ML87V2107
• OCLK-dividing synchronous generation --- 525-line mode
Mode setting conditions: VMD[1:0] = 0, ASYNC = 1, INT = 1, SVDL[10:0] = Don't care
[Setting VSYM[0] = 0]
From the internal TRG generation position (no delay adjustment by SVDL[10:0]), one vertical Sync. signal of 3
lines is generated in OVS following 3 lines and one vertical Sync. signal of 3 lines is generated following 262.5
lines.
[Setting VSYM[0] = 1]
From the internal TRG generation position (no delay adjustment by SVDL[10:0]), one vertical Sync. signal of
1.5 lines is generated following 4 lines and one vertical Sync. signal of 1.5 lines is generated following 262.5
lines.
The value that is set in SVDL[10:0] is invalid and equivalent to 000h.
Under the default condition (SFINV(SUB:68h-bit[2]) = 0), Sync. signals are generated twice for TRG input in
the sequence of field A and field B and under SFINV = 1, Sync. signals are generated twice in the sequence of
field A and field B.
TRG
[SFINV=0]
OHS
[SFINV=1]
OHS
262.5 lines
[VSYM[0]=0,OVSINV=0]
OVS
3 lines
3 lines
3 lines
3 lines
[VSYM[0]=0,OVSINV=1]
OVS
262.5 lines
[VSYM[0]=1,OVSINV=0]
OVS
4 lines
1.5 lines
4 lines
1.5 lines
[VSYM[0]=1,OVSINV=1]
OVS
OVS reset position
Figure F3-1-3(10) Vertical Direction Timing 8
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