FEDL87V2107-01
OKI Semiconductor
ML87V2107
• OCLK-dividing synchronous generation --- 625-line mode
Mode setting conditions: VMD[1:0] = 0, ASYNC = 1, INT = 0, SVDL[10:0] = Don't care
[Setting VSYM[0] = 0]
From the TRG generation position (no delay adjustment by SVDL[10:0]), one vertical Sync. signal of 2.5 lines
is generated in OVS following 2.5 lines and one vertical Sync. signal of 3 lines is generated following 312.5
lines.
[Setting VSYM[0] = 1]
From the TRG generation position (no delay adjustment by SVDL[10:0]), one vertical Sync. signal of 1.5 lines
is generated following 3.5 lines and one vertical Sync. signal of 1.5 lines is generated following 312.5 lines.
The value that is set in SVDL[10:0] is invalid and equivalent to 000h.
Under the default condition (SFINV(SUB:68h-bit[2]) = 0), Sync. signals are generated twice for TRG input in
the sequence of field A and field B and under SFINV = 1, Sync. signals are generated twice in the sequence of
field A and field B.
TRG
[SFINV=0]
OHS
[SFINV=1]
OHS
312.5 lines
[VSYM[0]=0,OVSINV=0]
OVS
2.5 lines 2.5 lines
2.5 lines 2.5 lines
[VSYM[0]=0,OVSINV=1]
OVS
312.5 lines
1.5 lines
[VSYM[0]=1,OVSINV=0]
OVS
3.5 lines
3.5 lines
1.5 lines
[VSYM[0]=1,OVSINV=1]
OVS
OVS reset position
Figure F3-1-3(9) Vertical Direction Timing 7
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