FEDL87V2107-01
OKI Semiconductor
ML87V2107
1.2.3 Setting Output System Valid Area
This IC generates the read enable signals (ORE) for reading data in the valid area made up of the valid vertical
lines and the valid horizontal pixels defined by the output control mode settings from the frame memory. With the
read enable, it is possible to set the starting point in the vertical and horizontal directions. This setting makes it
possible to line up the areas of valid lines and valid pixels with non-standard phase Sync. signals.
Normally, the valid number of lines that can be read from the memory is 288/243. However, by setting
VBID(SUB:41h-bit[3]) = 1 in ITU-R BT.656 mode, 304/254 lines can be selected as the valid number of lines.
However, the valid number of lines for noise reduction processing remains 288/243.
In 525i mode, normally the valid number of lines is 288/243. However, by setting AR241(SUB:72h-bit[4]) = 1,
the valid number of lines can be restricted to only 241 by disabling two lines of valid noise reduction processing
lines from the top.
Table F1-2-3(1) Valid Output Data Area
VMD
HMD
Valid lines
Valid pixels
[1]
0
[0]
0
[1]
0
[0]
0
288(304)
243(254)
288(304)
243(254)
288(304)
243(254)
720
720
768
640
768
768
0
1
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
Others
Test modes (not settable)
*: ( ) indicates only ITU-RBT.656 input/output mode can be selected.
288(304)/240(254)lines
OHS
#ORE
YO
CO
: Valid data
: Blanking data
Figure F1-2-3(1) Output Vertical Valid Lines
640/720/768pixels
OHS
#ORE
YO
CO
: Valid data
: Blanking data
Figure F1-2-3(2) Output Horizontal Valid Pixels
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