FEDL87V2107-01
OKI Semiconductor
ML87V2107
1.2.2 Input System Field Detection
This IC detects a field from the phases of output Sync. signals OVS and OHS and outputs optimum data from the
field memory.
The field detection pulse can be selected from the OHS (OFLS = 0) or from 0.5H pulse (OFLS = 1) by setting the
I2C-bus setting register OFLS (SUB:61h-bit[4]).
In the rear edge of judgment area, since the field judgment uncertainty area contains 10 clocks of OOCLK
(internal input system clock), external phase adjustment will be necessary if the phase of OVS lies in this area.
(However, there is no problem if the change of OVS and OHS is in the same phase.)
OVS
Field A detection
phase
OHS
Field A detection
phase
0.5H
Pulse
Figure F1-2-2(1) Field A Detection Timing
OVS
Field B detection
phase
OHS
Field B detection
phase
0.5H
Pulse
Figure F1-2-2(2) Field B Detection Timing
Field A judgment area
Field B judgment area
OHS
or
#0.5H Pulse
Field judgment margin (10 clocks)
Field judgment uncertainty area
Field judgment margin (10 clocks)
Field judgment uncertainty area
#: Internal pulse
Figure F1-2-2(3) Field Judgment Uncertainty Area
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