FEDL87V2107-01
OKI Semiconductor
ML87V2107
AR241 Initial value: 0; Setting range: 0 to 1
Sets the valid number of 525i mode lines.
This bit influences valid data signals that are output from the HREF pin.
Table R2-7-2(5) Setting of Valid Number of 525i Mode Lines
AR240
Data output
0
Valid 243 lines at 525i
Valid 241 lines at 525i
1
RLTG Initial value: 0; Setting range: 0 to 1
Sets the register setting synchronous mode. Normally 0, used only for tests.
Table R2-7-2 (6) Register Set Mode Setting
RLTG
Data reflection
IVS, OVS synchronous
When I2C-bus is set
0
1
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