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VT82C686B 参数 Datasheet PDF下载

VT82C686B图片预览
型号: VT82C686B
PDF下载: 下载PDF文件 查看货源
内容描述: PCI SUPER -I / O集成外设控制器 [PCI Super-I/O Integrated Peripheral Controller]
分类和应用: 控制器PC
文件页数/大小: 128 页 / 1074 K
品牌: ETC [ ETC ]
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VT82C686B  
USB-Specific Configuration Registers  
Offset 40 - Miscellaneous Control 1.................................RW  
Offset 41 - Miscellaneous Control 2 ................................ RW  
7
PCI Memory Command Option  
7
USB 1.1 Improvement for EOP  
0
Support Memory-Read-Line, Memory-Read-  
Multiple, & Memory-Write-&-Invalidate.... def  
Only support Mem Read, Mem Write Cmds  
0
USB Specification 1.1 Compliant.......... default  
If a bit stuffing error occurs before EOP, the  
receiver will accept the packet  
1
1
USB Specification 1.0 Compliant  
6
Babble Option  
0
Automatically disable babbled port when EOF  
babble occurs..........................................default  
If a bit stuffing error occurs before EOP, the  
receiver will ignore the packet  
1
Dont disable babbled port  
....................default = 0  
6-5 Reserved (Do Not Program)  
5
4
3
2
1
0
PCI Parity Check Option  
4
Hold PCI Request for Successive Accesses  
0
Disable PERR# generation.....................default  
0
Disable  
1
Enable parity check and PERR# generation  
1
Enable.................................................... default  
Frame Interval Select  
Setting this bit to enablecauses the system to treat  
the USB request as higher priority  
Frame Counter Test Mode  
0
1 ms frame..............................................default  
1
0.1 ms frame  
3
2
USB Data Length Option  
0
Disable................................................... default  
0
Support TD length up to 1280................default  
1
Enable  
1
Support TD length up to 1023  
Trap Option  
USB Power Management  
0
Set trap 60/64 status bits only when trap 60/64  
0
Disable USB power management...........default  
enable bits are set. ................................. default  
Set trap 60/64 status bits without checking  
enable bits  
1
Enable USB power management  
1
DMA Option  
0
8 DW burst access with better FIFO latencydef  
1
0
A20gate Pass Through Option  
1
16 DW burst access (original performance)  
0
Pass through A20GATE command sequence  
defined in UHCI .................................... default  
Dont pass through Write I/O port 64 (ff)  
PCI Wait States  
0
Zero wait ................................................default  
1
1
One wait  
USB IRQ Test Mode  
0
Normal Operation.................................. default  
1
Generate USB IRQ  
Revision 1.71 June 9, 2000  
-79-  
Function 3 Registers - USB Controller Ports 2-3  
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