VT82C686B
Offset 79-78 – PCS0# I/O Port Address ..........................RW
Offset 7F-7E – 32-Bit DMA Control............................... RW
15-0 PCS0# I/O Port Address [15-0]
15-3 32-Bit DMA High Page (A31-24) Registers IOBase
........................................always reads 0
2-1 Reserved
Offset 7B-7A – PCS1# I/O Port Address.........................RW
0
32-Bit DMA
15-0 PCS1# I/O Port Address [15-0]
0
1
Disable................................................... default
Enable
Offset 80 – Programmable Chip Select Mask ................ RW
Offset 7D-7C – PCI DMA Channel Enable.....................RW
7-4 PCS1# I/O Port Address Mask [3-0]
3-0 PCS0# I/O Port Address Mask [3-0]
........................................ always reads 0
15-9 Reserved
.................... default = 0
8-5 Reserved (Do Not Program)
........................................ always reads 0
4
Reserved
.................... default = 0
3-0 Reserved (Do Not Program)
Revision 1.71 June 9, 2000
-64-
Function 0 Registers - PCI to ISA Bridge
ETC [ ETC ]
