VT82C686B
Offset 76 – GPIO Control 3 (00) ......................................RW
Offset 77 – GPIO Control 4 Control (10h) ..................... RW
7
Over-Current (OC) Input
7
DRQ / DACK# Pins are GPI / GPO
0
1
Disable ...................................................default
Enable (pins G5 and H3 are USBOC0# and
USBOC1# if bit-6 = 0)
0
1
Disable................................................... default
Enable
6
Game Port XY Pins are GPI / GPO
0
Disable................................................... default
6
OC[3:0] From SD[3:0] By Scan
0
Disable (pins G5 & H3 are USBOC0# and
USBOC1# if bit-7 = 1)...........................default
Enable
1
Enable
........................................always reads 0
5
4
Reserved
Internal APIC Enable
1
0
1
Disable
5
4
3
GPO14 / GPO15 Enable (Pins E12 / D12)
0
Pins used for IRTX and IRRX ...............default
Enable (U10 = WSC#, V9 = APICD0, T10 =
APICD1)................................................ default
1
Pins used for GPO14 and GPO15
MCCS# Pin Select
3
2
1
0
IRQ0 Output
0
MCCS# is on Pin U5..............................default
0
1
Disable................................................... default
Enable IRQ0 output to GPIOC
1
MCCS# is on Pin U8
MCCS# Function
RTC Rx32 Write Protect
0
Disable MCCS# function .......................default
0
1
Disable................................................... default
Enable
1
Enable MCCS# function
(see bit-4 for select of U5 or U8 for MCCS#)
CHAS Enable (Pin V14)
RTC Rx0D Write Protect
0
1
Disable................................................... default
Enable
2
1
0
0
Pin is defined as GPIOC.........................default
1
Pin is defined as CHAS
GPO13 Enable (Pin U5)
0
1
Pin defined as SOE#.............................. default
Pin defined as GPO13
GPO12 Enable (Pin T5)
0
Pin is defined as XDIR...........................default
1
Pin is defined as GPO12
GPOWE# (GPO[23-16]) Enable (Pin T14)
0
1
Pin is defined as GPIOA ........................default
Pin is defined as GPOWE# (Rx74[2] also must
be set to 1)
Revision 1.71 June 9, 2000
-63-
Function 0 Registers - PCI to ISA Bridge
ETC [ ETC ]
