VT82C686B
Table 3. Registers
Legacy I/O Registers
Port Master DMA Controller Registers Default Acc
Legacy I/O Registers (continued)
Port DMA Page Registers
Default Acc
RW
00 Channel 0 Base & Current Address
01 Channel 0 Base & Current Count
02 Channel 1 Base & Current Address
03 Channel 1 Base & Current Count
04 Channel 2 Base & Current Address
05 Channel 2 Base & Current Count
06 Channel 3 Base & Current Address
07 Channel 3 Base & Current Count
08 Status / Command
09 Write Request
0A Write Single Mask
0B Write Mode
0C Clear Byte Pointer FF
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
WO
WO
WO
RW
87 DMA Page – DMA Channel 0
83 DMA Page – DMA Channel 1
81 DMA Page – DMA Channel 2
82 DMA Page – DMA Channel 3
8F DMA Page – DMA Channel 4
8B DMA Page – DMA Channel 5
89 DMA Page – DMA Channel 6
8A DMA Page – DMA Channel 7
RW
RW
RW
RW
RW
RW
RW
Port System Control Registers
92 System Control
Default Acc
RW
Port Slave Interrupt Controller Regs
A0 Slave Interrupt Control
A1 Slave Interrupt Mask
A0 Slave Interrupt Control Shadow
A1 Slave Interrupt Mask Shadow
* RW accessible if shadow registers are disabled
Default Acc
—
—
—
—
*
*
RW
RW
0D Master Clear
0E Clear Mask
0F Read / Write Mask
Port Master Interrupt Controller Regs
20 Master Interrupt Control
21 Master Interrupt Mask
20 Master Interrupt Control Shadow
21 Master Interrupt Mask Shadow
* RW if shadow registers are disabled
Default Acc
—
—
—
—
*
*
RW
RW
Port Slave DMA Controller Registers
C0 Channel 0 Base & Current Address
C2 Channel 0 Base & Current Count
C4 Channel 1 Base & Current Address
C6 Channel 1 Base & Current Count
C8 Channel 2 Base & Current Address
CA Channel 2 Base & Current Count
CC Channel 3 Base & Current Address
CE Channel 3 Base & Current Count
D0 Status / Command
Default Acc
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port Timer/Counter Registers
40 Timer / Counter 0 Count
41 Timer / Counter 1 Count
42 Timer / Counter 2 Count
43 Timer / Counter Control
Default Acc
RW
RW
RW
WO
D2 Write Request
D4 Write Single Mask
D6 Write Mode
D8 Clear Byte Pointer FF
DA Master Clear
DC Clear Mask
DE Read / Write Mask
WO
WO
WO
WO
WO
WO
RW
Port Keyboard Controller Registers
60 Keyboard Controller Data
61 Misc Functions & Speaker Control
64 Keyboard Ctrlr Command / Status
Default Acc
RW
RW
RW
Port CMOS / RTC / NMI Registers
70 CMOS Memory Address & NMI Disa
71 CMOS Memory Data (128 bytes)
72 CMOS Memory Address
Default Acc
WO
RW
RW
73 CMOS Memory Data (256 bytes)
74 CMOS Memory Address
RW
RW
75 CMOS Memory Data (256 bytes)
RW
NMI Disable is port 70h (CMOS Memory Address) bit-7.
RTC control occurs via specific CMOS data locations (0-Dh).
Ports 72-73 may be used to access all 256 locations of CMOS.
Ports 74-75 may be used to access CMOS if the internal RTC
is disabled.
Revision 1.71 June 9, 2000
-28-
Register Overview
ETC [ ETC ]
