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VT82C686B 参数 Datasheet PDF下载

VT82C686B图片预览
型号: VT82C686B
PDF下载: 下载PDF文件 查看货源
内容描述: PCI SUPER -I / O集成外设控制器 [PCI Super-I/O Integrated Peripheral Controller]
分类和应用: 控制器PC
文件页数/大小: 128 页 / 1074 K
品牌: ETC [ ETC ]
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VT82C686B  
UltraDMA-33 / 66 / 100 Enhanced IDE Interface  
Signal Name  
Pin #  
I/O Signal Description  
/
N16  
I
EIDE Mode:  
UltraDMA Mode:  
Device ready indicator  
PDRDY  
Primary I/O Channel Ready.  
. Output flow control. The device  
Primary Device DMA Ready  
PDDMARDY /  
PDSTROBE  
may assert DDMARDY to pause output transfers  
. Input data strobe (both edges). The  
Primary Device Strobe  
device may stop DSTROBE to pause input data transfers  
/
V20  
N17  
W19  
N18  
I
EIDE Mode:  
UltraDMA Mode:  
Device ready indicator  
SDRDY  
Secondary I/O Channel Ready.  
SDDMARDY /  
SDSTROBE  
.
Output flow control. The  
Secondary Device DMA Ready  
device may assert DDMARDY to pause output transfers  
. Input data strobe (both edges). The  
device may stop DSTROBE to pause input data transfers  
Device read strobe  
. Primary channel input flow control  
The host may assert HDMARDY to pause input transfers  
. Output data strobe (both edges). The  
host may stop HSTROBE to pause output data transfers  
Device read strobe  
. Input flow control. The host  
may assert HDMARDY to pause input transfers  
Secondary Device Strobe  
/
O
O
O
EIDE Mode:  
UltraDMA Mode:  
PDIOR#  
PHDMARDY /  
PHSTROBE  
Primary Device I/O Read.  
Primary Host DMA Ready  
.
Primary Host Strobe  
/
EIDE Mode:  
UltraDMA Mode:  
SDIOR#  
Secondary Device I/O Read.  
Secondary Host DMA Ready  
SHDMARDY /  
SHSTROBE  
. Output strobe (both edges). The host may stop  
HSTROBE to pause output data transfers  
Host Strobe B  
/
/
EIDE Mode:  
UltraDMA Mode:  
Device write strobe  
Stop transfer: Asserted by the host prior to  
initiation of an UltraDMA burst; negated by the host before data  
is transferred in an UltraDMA burst. Assertion of STOP by the  
host during or after data transfer in UltraDMA mode signals the  
termination of the burst.  
PDIOW#  
Primary Device I/O Write.  
.
Primary Stop  
PSTOP  
W20  
O
EIDE Mode:  
Device write strobe  
SDIOW#  
Secondary Device I/O Write.  
SSTOP  
UltraDMA Mode:  
. Stop transfer: Asserted by the host prior to  
Secondary Stop  
initiation of an UltraDMA burst; negated by the host before data  
is transferred in an UltraDMA burst. Assertion of STOP by the  
host during or after data transfer in UltraDMA mode signals the  
termination of the burst.  
N19  
Y20  
M20  
V19  
L1  
I
I
O
O
I
Primary channel DMA request  
Secondary channel DMA request  
PDDRQ  
SDDRQ  
PDDACK#  
SDDACK#  
IRQ14  
Primary Device DMA Request.  
Secondary Device DMA Request.  
Primary Device DMA Acknowledge.  
Secondary Device DMA Acknowledge.  
Primary Channel Interrupt.  
Primary channel DMA acknowledge  
Secondary channel DMA acknowledge  
K5  
I
IRQ15  
Secondary Channel Interrupt.  
Revision 1.71 June 9, 2000  
-12-  
Pinouts  
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